FPGA Programming on the USRP with the RFNoC Framework

 

Tuesday, July 31, 2018

8:30 AM – 6:00 PM

 

IIIT Delhi

Okhla Phase 3, Near Govindpuri Metro Station,

New Delhi,

 
Ettus Research's RFNoC (RF Network-on-Chip) software framework is designed to decrease the development time for experienced FPGA engineers seeking to integrate IP into the USRP FPGA signal processing chain. RFNoC is the framework for USRP devices that use Xilinx 7-series FPGAs (E310, E312, X300, X310). RFNoC is built around a packetized network infrastructure in the FPGA that handles the transport of control and sample data between the host CPU and the radio. Users target their custom algorithms to the FPGA in the form of Computation Engines (CE), which are processing blocks that attach to this network. CEs act as independent nodes on the network that can receive and transmit data to any other node (e.g., another CE, the radio block, or the host CPU). Users can create modular, FPGA-accelerated SDR applications by chaining CEs into a flow graph. RFNoC is supported in UHD and GNU Radio. In this workshop, we will present an interactive hands-on tutorial on RFNoC, including a discussion on its design and capabilities, demonstrations of several existing examples, and a walk-through on implementing a user-defined CE and integrating the CE into GNU Radio.
 
For more details please visit - https://www.ettus.com/OSSDR-workshops
 
For any queries please write to karamvir.rathi@ni.com